Struct cranelift_codegen::machinst::vcode::VCode

pub struct VCode<I: VCodeInst> { /* fields omitted */ }

A function in “VCode” (virtualized-register code) form, after lowering. This is essentially a standard CFG of basic blocks, where each basic block consists of lowered instructions produced by the machine-specific backend.

Implementations

impl<I: VCodeInst> VCode<I>

pub fn flags(&self) -> &Flags

Returns the flags controlling this function’s compilation.

pub fn vreg_type(&self, vreg: VirtualReg) -> Type

Get the IR-level type of a VReg.

pub fn have_ref_values(&self) -> bool

Are there any reference-typed values at all among the vregs?

pub fn entry(&self) -> BlockIndex

Get the entry block.

pub fn num_blocks(&self) -> usize

Get the number of blocks. Block indices will be in the range 0 .. (self.num_blocks() - 1).

pub fn frame_size(&self) -> u32

Stack frame size for the full function’s body.

pub fn stack_args_size(&self) -> u32

Inbound stack-args size.

pub fn succs(&self, block: BlockIndex) -> &[BlockIx]

Get the successors for a block.

pub fn replace_insns_from_regalloc(&mut self, result: RegAllocResult<Self>)

Take the results of register allocation, with a sequence of instructions including spliced fill/reload/move instructions, and replace the VCode with them.

pub fn emit(&self) -> MachBuffer<I> where
    I: MachInstEmit, 

Emit the instructions to a MachBuffer, containing fixed-up code and external reloc/trap/etc. records ready for use.

pub fn unwind_info(&self) -> CodegenResult<Option<UnwindInfo<Reg>>>

Generates unwind info.

pub fn bindex_to_bb(&self, block: BlockIndex) -> Option<Block>

Get the IR block for a BlockIndex, if one exists.

Trait Implementations

impl<I: VCodeInst> Debug for VCode<I>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<I: VCodeInst> Function for VCode<I>

type Inst = I

Regalloc is parameterized on F: Function and so can use the projected type F::Inst.

fn insns(&self) -> &[I]

Allow access to the underlying vector of instructions.

fn insns_mut(&mut self) -> &mut [I]

Allow mutable access to the underlying vector of instructions.

fn get_insn(&self, insn: InstIx) -> &I

Get an instruction with a type-safe InstIx index.

fn get_insn_mut(&mut self, insn: InstIx) -> &mut I

Get a mutable borrow of an instruction with the given type-safe InstIx index.

fn blocks(&self) -> Range<BlockIx>

Allow iteration over basic blocks (in instruction order).

fn entry_block(&self) -> BlockIx

Get the index of the entry block.

fn block_insns(&self, block: BlockIx) -> Range<InstIx>

Provide the range of instruction indices contained in each block.

fn block_succs(&self, block: BlockIx) -> Cow<'_, [BlockIx]>

Get CFG successors for a given block.

fn is_ret(&self, insn: InstIx) -> bool

Determine whether an instruction is a return instruction.

fn is_included_in_clobbers(&self, insn: &I) -> bool

Determine whether an instruction should be considered while computing the set of registers that need to be saved/restored in the function’s prologue/epilogue, that is, the registers returned in clobbered_registers in RegAllocResult. computation. Only instructions for which this function returns true will be used to compute that set.

fn get_regs(insn: &I, collector: &mut RegUsageCollector<'_>)

Add to collector the used, defined, and modified registers for an instruction.

fn map_regs<RUM: RegUsageMapper>(insn: &mut I, mapper: &RUM)

Map each register slot through a virtual-to-real mapping indexed by virtual register. The two separate maps in maps.pre and maps.post provide the mapping to use for uses (which semantically occur just prior to the instruction’s effect) and defs (which semantically occur just after the instruction’s effect). Regs that were “modified” can use either map; the vreg should be the same in both.

fn is_move(&self, insn: &I) -> Option<(Writable<Reg>, Reg)>

Allow the regalloc to query whether this is a move. Returns (dst, src).

fn get_num_vregs(&self) -> usize

Get the precise number of VirtualReg in use in this function, to allow preallocating data structures. This number must be a correct lower-bound, otherwise invalid index failures may happen; it is of course better if it is exact.

fn get_spillslot_size(&self, regclass: RegClass, vreg: VirtualReg) -> u32

How many logical spill slots does the given regclass require? E.g., on a 64-bit machine, spill slots may nominally be 64-bit words, but a 128-bit vector value will require two slots. The regalloc will always align on this size.

fn gen_spill(
    &self,
    to_slot: SpillSlot,
    from_reg: RealReg,
    vreg: Option<VirtualReg>
) -> I

Generate a spill instruction for insertion into the instruction sequence. The associated virtual register (whose value is being spilled) is passed, if it exists, so that the client may make decisions about the instruction to generate based on the type of value in question. Because the register allocator will insert spill instructions at arbitrary points, the returned instruction here must not modify the machine’s condition codes.

fn gen_reload(
    &self,
    to_reg: Writable<RealReg>,
    from_slot: SpillSlot,
    vreg: Option<VirtualReg>
) -> I

Generate a reload instruction for insertion into the instruction sequence. The associated virtual register (whose value is being loaded) is passed as well, if it exists. The returned instruction must not modify the machine’s condition codes.

fn gen_move(
    &self,
    to_reg: Writable<RealReg>,
    from_reg: RealReg,
    vreg: VirtualReg
) -> I

Generate a register-to-register move for insertion into the instruction sequence. The associated virtual register is passed as well. The returned instruction must not modify the machine’s condition codes.

fn gen_zero_len_nop(&self) -> I

Generate an instruction which is a no-op and has zero length.

fn maybe_direct_reload(
    &self,
    insn: &I,
    reg: VirtualReg,
    slot: SpillSlot
) -> Option<I>

Try to alter an existing instruction to use a value directly in a spillslot (accessing memory directly) instead of the given register. May be useful on ISAs that have mem/reg ops, like x86.

fn func_liveins(&self) -> RegallocSet<RealReg>

Return the set of registers that should be considered live at the beginning of the function. This is semantically equivalent to an instruction at the top of the entry block def’ing all registers in this set.

fn func_liveouts(&self) -> RegallocSet<RealReg>

Return the set of registers that should be considered live at the end of the function (after every return instruction). This is semantically equivalent to an instruction at each block with no successors that uses each of these registers.

pub fn insn_indices(&self) -> Range<InstIx>

Get all instruction indices as an iterable range.

impl<I: VCodeInst> PrettyPrint for VCode<I>

Pretty-printing with RealRegUniverse context.

fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String

Return a string that shows the implementing object in context of the given RealRegUniverse, if provided.