Trait cranelift_codegen::machinst::lower::LowerBackend[−][src]

pub trait LowerBackend {
    type MInst: VCodeInst;
    fn lower<C: LowerCtx<I = Self::MInst>>(
        &self, 
        ctx: &mut C, 
        inst: Inst
    ) -> CodegenResult<()>;

    fn lower_branch_group<C: LowerCtx<I = Self::MInst>>(
        &self, 
        ctx: &mut C, 
        insts: &[Inst], 
        targets: &[MachLabel]
    ) -> CodegenResult<()>;

    fn maybe_pinned_reg(&self) -> Option<Reg> { ... }
}

A machine backend.

Associated Types

type MInst: VCodeInst[src]

The machine instruction type.

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Required methods

fn lower<C: LowerCtx<I = Self::MInst>>(
    &self,
    ctx: &mut C,
    inst: Inst
) -> CodegenResult<()>[src]

Lower a single instruction.

For a branch, this function should not generate the actual branch instruction. However, it must force any values it needs for the branch edge (block-param actuals) into registers, because the actual branch generation (lower_branch_group()) happens after any possible merged out-edge.

fn lower_branch_group<C: LowerCtx<I = Self::MInst>>(
    &self,
    ctx: &mut C,
    insts: &[Inst],
    targets: &[MachLabel]
) -> CodegenResult<()>[src]

Lower a block-terminating group of branches (which together can be seen as one N-way branch), given a vcode MachLabel for each target.

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Provided methods

fn maybe_pinned_reg(&self) -> Option<Reg>[src]

A bit of a hack: give a fixed register that always holds the result of a get_pinned_reg instruction, if known. This allows elision of moves into the associated vreg, instead using the real reg directly.

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Implementors

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